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Job Requirements of Network-on-chip (NoC)/ Interconnect Design Engineer(RTL):
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Employment Type:
Full-Time
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Experience:
Not Specified
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Education:
Not Specified
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Travel:
Not Specified
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Manage Others:
Not Specified
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Location:
Bengaluru, Karnataka (Onsite)
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Network-on-chip (NoC)/ Interconnect Design Engineer(RTL)
Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
Network-on-chip (NoC)/ Interconnect Design and Architecture for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. The roles and responsibilities for this position includes but not limited to:-
Design for Next-gen Qualcomm coherent and non-coherent interconnect fabric
Responsible for specification, Micro-Arch, design and implementation of interconnect and related IP’s
Actively work with SoC Architecture, verification, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites
Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions
Responsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues
Will be part of BDC infrastructure (NoC/Interconnect) core team
Minimum Qualifications:
10+ years of solid experience in IP/SoC design
Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
Good knowledge of Digital Design and RTL development
Hands-on experience with SoC Design, Verilog RTL coding
Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.
Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
Working knowledge of Lint, CDC, PLDRC, CLP etc
Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Manage SoC dependencies, planning and tracking of all front-end design related tasks
Driving the project milestones across the design, verification and physical implementations
Should possess effective communication and leadership skills
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to
Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found
for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.Qualcomm is an equal opportunity employer and supports workforce diversity.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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If you would like more information about this role, please contact
. ]]>Recommended Skills
- Advanced Microcontroller Bus Architecture
- Architecture
- Communication
- Debugging
- Floor Planning
- Formal Verification
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