Standard Cell Layout Engineer

Company:

Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

Job Function -  We are looking for a Standard cell Layout expertise in 14nm, 10nm, 7nm, 5nm, 4nm & 3nm. This position would allow to work in the cutting edge of semiconductor technology - redefining the library every 6-12 months (architecture & cell offering).

The Candidate will be responsible for layout design of standard cell, Power management, ECO and custom cell.  Follow design guidelines set forth by the Engineering and Layout design leads in delivering high quality deliverables in a timely manner.

Skills/Exp   -2-5 years of experience in VLSI layout design or ASIC design. In-depth proficiency in deep sub-micron FinFET technologies 14nm, 10nm, 7nm, 5nm, 4nm & 3nm is strongly desired. Good understanding of the standard cell library development & architecture, ASIC design flow, semi-custom design flows and physical verification tools. Proficient in DRC, LVS, ERC, Density cleanup and worked on DFM checks Litho, PM, MAS

Tools                     Cadence Virtuoso/VXL, Calibre verification tools & Calibre RVE.

Scripting              Skill, Perl & Shell

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to 

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found

for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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